Urgent! RTL Design Engineering Internship Job Opening In Rennes – Now Hiring Silicon Labs
Our Engineers solve real-world problems within a highly collaborative team of the industry’s most innovative talent.
As a Silicon Labs Intern, you will help create and extend our offering of wireless solutions for smart cities.
We count among our customers some of the most recognized and well-respected companies in the world, and innovators in IoT.
You will be part of a highly skilled and tight-knit team where everyone has a significant impact on, and responsibility for, the end product.
The Rennes site is cross-functional and therefore you’ll be part or interacting firsthand with chip and embedded software designers or customer application team.
Silicon Labs is a global company, and you’ll have regular interactions with our extended teams across the world.
We strive to strike a good work/life balance and make our environment welcoming and fun, so we seek someone whose technical skills are matched by their interpersonal skills.
What You’ll Do
Projects are specifically tailored to each intern, ensuring a meaningful contribution to both your skillset and Silicon Labs.
Within our DSP design team, in charge of studying new modem algorithms and architecture, anticipating future needs, you will study possibilities offered by different kind of channel coding schemes.
In IOT standards, we see emerging needs of transmission for long-range / low data-rate, small packets with strong and efficient encoding.
Based on an existing RTL code for a Front-End (FE) filtering block you will make the necessary adaptations of the specifications to suit a new application and analyze possible optimizations.
Using the above FE block as a reference implementation you will study the feasibility of using GenAI tools for RTL code analysis (find bugs, propose optimizations) and generation (propose a new implementation).
You will evaluate the capability as well of GenAI for testbench generation and verification of a block.
If time allows it, you will also develop (with assistance from GenAI) the RTL code for a small NPU (Neural Processing Unit) that will be used to implement a Signal Processing task (e.g., preamble detection) using Machine Learning techniques.
Your tasks will spread over different subjects, function of your expectation, our needs and evolution of the project:
Analyze and develop RTL code unassisted at first, and then with the help of GenAI tools
Simulate in Matlab the performance of the FE and compare with RTL implementation
Assess performance vs area tradeoffs in state-of-the-art systems developed by Silicon Labs for future products
Assist in evaluating the feasibility of Machine Learning techniques for Signal Processing (focus on RTL implementation)
Who You Are
You are an innovator, builder, and tinkerer.
You have a curious mind and a drive to succeed.
You want to work with a global team of technology enthusiasts and design pioneers.
Here’s what you need:
You are in the last year of a Master's degree in computer science, computer engineering, electrical engineering, electronics, or similar
You have some combination of the following skills:
RTL Design: Verilog, System Verilog, VHDL
Digital Design: Signal processing (filtering, FIR, IIR, etc.), Digital Communications
Software: Matlab, Python, Embedded C, Scripting
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Unlock Your RTL Design Potential: Insight & Career Growth Guide
Real-time RTL Design Jobs Trends in Rennes, France (Graphical Representation)
Explore profound insights with Expertini's real-time, in-depth analysis, showcased through the graph below. This graph displays the job market trends for RTL Design in Rennes, France using a bar chart to represent the number of jobs available and a trend line to illustrate the trend over time. Specifically, the graph shows 433 jobs in France and 8 jobs in Rennes. This comprehensive analysis highlights market share and opportunities for professionals in RTL Design roles. These dynamic trends provide a better understanding of the job market landscape in these regions.
Great news! Silicon Labs is currently hiring and seeking a RTL Design Engineering Internship to join their team. Feel free to download the job details.
Wait no longer! Are you also interested in exploring similar jobs? Search now: RTL Design Engineering Internship Jobs Rennes.
An organization's rules and standards set how people should be treated in the office and how different situations should be handled. The work culture at Silicon Labs adheres to the cultural norms as outlined by Expertini.
The fundamental ethical values are:The average salary range for a RTL Design Engineering Internship Jobs France varies, but the pay scale is rated "Standard" in Rennes. Salary levels may vary depending on your industry, experience, and skills. It's essential to research and negotiate effectively. We advise reading the full job specification before proceeding with the application to understand the salary package.
Key qualifications for RTL Design Engineering Internship typically include Engineers and a list of qualifications and expertise as mentioned in the job specification. Be sure to check the specific job listing for detailed requirements and qualifications.
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Here are some tips to help you prepare for and ace your job interview:
Before the Interview:To prepare for your RTL Design Engineering Internship interview at Silicon Labs, research the company, understand the job requirements, and practice common interview questions.
Highlight your leadership skills, achievements, and strategic thinking abilities. Be prepared to discuss your experience with HR, including your approach to meeting targets as a team player. Additionally, review the Silicon Labs's products or services and be prepared to discuss how you can contribute to their success.
By following these tips, you can increase your chances of making a positive impression and landing the job!
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